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8 Mbit 1.8V SPI Serial Flash
A Microchip Technology Company
SST25WF080
Not Recommended for New Designs
5. 64 KByte Block-Erase addresses: use A MS -A 16, remaining addresses are don’t care but must be set either at V IL or V IH.
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of
data to be programmed. Data Byte 0 will be programmed into the initial address [A 23 -A 1 ] with A 0 =0, Data Byte 1 will be
programmed into the
initial address [A 23 -A 1 ] with A 0 = 1.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
8. Either EWSR or WREN followed by WRSR will write to the Status register. The EWSR-WRSR sequence provides back-
ward compatibility to the SST25VF/LF series. The WREN-WRSR sequence is recommended for new designs.
9. Manufacturer’s ID is read with A 0 =0, and Device ID is read with A 0 =1. All other address bits are 00H. The Manufac-
turer’s ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#.
Read (33 MHz)
The Read instruction, 03H, supports up to 33 MHz Read. The device outputs a data stream starting
from the specified address location. The data stream is continuous through all addresses until termi-
nated by a low-to-high transition on CE#. The internal address pointer automatically increments until
the highest memory address is reached. Once the highest memory address is reached, the address
pointer automatically increments to the beginning (wrap-around) of the address space. For example,
for 8 Mbit density, once the data from the address location FFFFFH is read, the next output is from
address location 000000H. The Read instruction is initiated by executing an 8-bit command, 03H, fol-
lowed by address bits A 23 -A 0 . CE# must remain active low for the duration of the Read cycle. See Fig-
ure 7 for the Read sequence.
CE#
MODE 3
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47
48
55 56
63 64
70
SCK
MODE 0
SI
03
ADD.
ADD.
ADD.
SO
MSB
MSB
HIGH IMPEDANCE
N
D OUT
N+1
DOUT
N+2
D OUT
N+3
D OUT
N+4
D OUT
Figure 7: Read Sequence
MSB
1203 F06.0
?2012 Silicon Storage Technology, Inc.
12
DS25024B
03/12
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